This invention relates to metal oxide semiconductor field effect transistors (MOSFETS), and more specifically relates to a novel configuration for a high power MOSFET device and a novel process for its manufacture.
High power MOSFETS having low on-resistance and relatively high breakdown voltage are known and are typically shown in any of the related applications referred to above. Thus, the device of co-pending application Ser. No. 178,689 provides a high power MOSFET device with low forward resistance and high packing density for individual cell elements which are connected in parallel to form the device. Moreover, the device can be made with D-MOS fabrication techniques and has a relatively low gate capacitance.
The individual cells of known devices have respective source regions which are polygonal, and are preferably hexagonal, to ensure a constant spacing between the major lengths of adjacent sources disposed over the surface of the chip of wafer. Each of the hexagonal regions has a width measured perpendicularly to the two opposing sides of the hexagon which they define of less than about 1 ml and are spaced from one another by about 0.6 mil when measured perpendicularly between the adjacent straight sides of adjacent polygonal regions. An extremely large number of small hexagonal source elements may be formed in the same surface of the semiconductor body for a given device. For example, 6,600 hexagonal source regions have been formed in a chip area having a dimension of about 100 by 140 mils to produce an effective channel width of about 22,000 mils. This produces a device having very high current capacity and low forward resistance.
A polysilicon gate may be used which has a hexagonal grid-like configuration which is disposed atop a corresponding gate oxide layer. Each leg of the gate oxide grid overlies two spaced channels which are capable of inversion by application of a voltage to the polysilicon gate. The gate structure is then contacted over the upper surface of the device by symmetric, elongated gate contact fingers which ensure good contact over the full surface of the gate.
Each of the polygonal source regions is contacted by a continuous conductive source contact layer or sheet which engages the individual polygonal sources through openings in an insulation layer covering the source regions. These openings can be formed by conventional D-MOS photolithographic techniques. A source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate fingers. A drain connection region is made to the reverse surface of the semiconductor device.
During conduction, current from the individual source regions flow through the surrounding respective channels into the upper web-shaped portion of the common region which extends vertically through the thickness of the chip to the bottom drain electrode. Preferably, the upper portion of this web has a high conductive in order to decrease the on-resistance of the device by reducing spreading resistance and bulk resistance. The higher conductivity also reduces the effect of the parasitic bipolar transistor formed by the three alternate conductivity regions which is inherently defined in the device. Preferably, this high conductivity common region has a constant impurity concentration laterally across the full width of the device, as is disclosed in above-noted co-pending application Ser. No. 178,689.
Each of the source elements described above is formed in its own respective channel or base region. Typically in an N channel, enhancement mode MOSFET device, the channel or base region is a P type region which extends into the surface of the chip, with a polygonal source region diffused or otherwise formed into this base region. The base region is preferably relatively highly conductive in order to prevent turning on of a parasitic bipolar transistor which is formed by the three sequential regions of the device which would inject a destructive current and energetic electrons into the gate region which reduces the ruggedness of the device. By ruggedness, is meant the ability of the device to resist damage or destruction due to energetic electrons in the gate region, both in avalanche and during forward conduction. In the center of each cell was a deeper P+ type region of about 5 microns as compared to a 3 micron depth for the outer periphery of the bottom of the base regions. This deeper and more highly conductive P+ region served to increase the conductance of, and reduce the contact resistance to, the base region of the parasitic bipolar transistor.
The use of the increased depth region in the base, however, complicates the manufacturing process because it requires a separate mask during the manufacturing process, and adequate area to allow for side-diffusion of the deep P+ section. The additional mask imposes a limitation on the maximum reduction of cell size for a given set of tolerances, since cell size must be increased to accommodate manufacturing tolerances for each additional mask which is used in the process of forming the cell. Thus, when using the additional mask to form the central deeper section of the P+ base region, the minimum cell size which could be obtained was about 38 microns in lateral dimension.